UVM interview questions and answers

How many phases UVM has explain each :-

1. We call run_test (if you don’t remember, see the line 17 of the top module in Tasting), which in turn calls the run_test task of the uvm_root class.
2. The uvm_root calls the m_run_phases task of the uvm_phase class.
3. For each phase, the execute_phase task is called.
4. If the phase is a top-down or bottom-up phase, exec_func is called for each component.
5. For example, the exec_func calls the build_phase function of each component.
6. If the phase is a task phase, exec_task is called for each component.
7. For example, the exec_task calls the main_phase task of each component.
8. The uvm_phase checks if any objections are raised by the components. The phase_done is the uvm_objection object that the uvm_phase keeps track of the number of objections with. When we called phase.raise_objection() from inside the run_phase of the jelly_bean_test class (see the line 27 of the jelly_bean_test class in Tasting), phase_done.raise_objection() is called in the uvm_phase under the hood.
9. If no objection is raised, all the processes started by the exec_task are killed. In other words, unless an objection is raised, the phase is immediately killed!
10. The steps 3 to 9 repeat until all phases are executed.

Why Final_phase is toptodown();

The final_phase() exists in UVM only for arrangements which run multiple loops around run..extract..check..report phases in a loop and then jump back to run() for the next iteration of multiple concatenated tests. Support for this is only partially defined or implemented in UVM today and is unlikely to be widely used in the industry (I would not recommend it for any use model that I am aware of).
However if this technique is used, there is a need for a final_phase() which is guaranteed to be the last phase before simulation exits, unlike report_phase() which may loop back. Why top-down? If one used this looped multiple test arrangement, final_phase() would be used for any cleanup required outside the loop, and hence it is top down, to ensure control from the topmost level of your test environment of that multiple test loop

Why build phase and connect phase is top to down and bottom to up ?

The build_phase has to be top-down because the parent component creates the child components (not the other way around). It also allows the parent component to configure the child components. On the other hand, the connect_phase, for example, is bottom-up. It allows the parent component to verify that the child components are connected properly.

http://cluelogic.com/2014/08/uvm-tutorial-for-candy-lovers-phasing/

How objection mechanism works 

How virtual sequence and virtual sequencer works ?

What is new,create ,build ?

• The new function creates an object of jelly_bean_agent. It also creates the handles for uvm_analysis_port, jelly_bean_sequencer, jelly_bean_driver, and jelly_bean_monitor. However, these handles are null because we have not created the objects for them yet.
• The build_phase function creates the components mentioned above. We called new to create an object of uvm_analysis_port. However, we called create to create the other components in case we want to override the component type later.
• The create function asks the UVM factory to create an object. The UVM factory knows which component to create even if the component type is overridden. The factory (or to be precise, uvm_component_registry) will call new on behalf of you.

How TLM works ?