Frequently asked AMBA AHB interview question

1. Why is there a 1KB restriction in AHB?

1KB is not a constraint for slave size, many of us get confused that AHB supports only 1KB slave size, In real definition 1KB is a restriction for burst transfer, the user is not allowed to send more than 1KB transfer size in one shot. The limit is designed to prevent bursts crossing from one device to another and to give a reasonable trade-off between burst size and efficiency. In practice, this means that a master must ALWAYS break a burst that would otherwise cross the 1KB boundary and restart it with a non-sequential transfer. 

The other way to understand, the master doesn't know the slave size and it doesn't want to any wrong transfer, either 1 slave with size 16K or 16 slaves with 1K  , the master will restart transfer after completing 1K transfer for a correct data transfer.  

Address: 0x3F0 0x3F4 0x3F8 0x3FC 0x400 0x404 0x408
Transfer: NSEQ SEQ    SEQ   SEQ    NSEQ  SEQ   SEQ 


2. Can BUSY state can come at the end of burst . 
An undefined length burst has no defined length, so a BUSY transfer could be inserted at any point after the initial NONSEQ access, and the master could end this burst on a BUSY. Probably the only time you could not add a BUSY in an undefined length burst is when the burst reaches a 1kB boundary, when you would need ot end the burst and either start a new burst with a NONSEQ, or insert IDLE cycles instead of any BUSY you might have wanted to insert.

A BUSY transfer cannot occur at the end of a fixed length burst (SINGLE, INCR4, WRAP4, INCR8, WRAP8, INCR16, WRAP16).

3. Can a master change the address/control signals during awaited transfer?

Yes. If the address/control signals are indicating an IDLE transfer then the master can change to a real transfer (NONSEQ) when HREADY is low.

However, if a master is indicating a real transfer (NONSEQ or SEQ) then it cannot cancel this during awaited transfer unless it receives a SPLIT, RETRY or ERROR response.

4. When can Early Burst Termination occur

the master can not terminate the burst by its own, it can be terminated only by two way.

1. Arbiter removing the HGRANT to a master part way through a burst.

2. Slave has given nonokay response for a beat of a burst . 

5. What is default Slave ?
For example memory address is only available from 2000 - 3000 , if the access is going  different from this region still we see a response it can be OKAY or ERROR , but question is from where it comes . the answer is there is a slave which does the job when no slave is presented . in case of HTRANS is IDEL/BUSY response will be OK , else it will be error . Default is not for access it just notify you that your transactions are in no mans land !! 

6. How to use a AMBA vip in verification environment ?

VIP generally used in two ways either your simulation tool will have a pulgins for it , like questa has AHB AXI support as far i know , or u need to integrate the VIP . 

Generally, we have ahb slave and master wrapper from the VIP team, these wrappers are connected to the top test bench file with DUT and test bench connections. than in the environment, we connect the agent.  Then sequence writing comes into picture . Sequence writing is a coding translation of the test flow of a test case . mostly test are doing clock set , reset deep sleep , wait for interrupt or trigger register writes or bus write and read  . these bus and register writes are happening using the ahb or apb connection. If any test gets fail the first thing we open is AHB or apb related signals .