How to coordinate sequence and test objection

#1 raise& drop should be in pre+post body because those functions are ONLY called when the sequence is "started" (aka a root sequence). a subsequence doesnt call pre/post body and therefore doesnt work change the objection count. so as a rule of thumb you would have as much objections as you would have active root sequences. (reactive) sequences such as for slaves and background functionality do not need objections.

#2 if your sequences are non-blocking you got some options:

- first you could wait for the responses to appear after the final sequences have been send

- second you could use a drain time to let your simulation complete after all objections have been dropped

- you could also have the scoreboard, the monitor or driver raising objections to prevent your simulation to stop too early

#3 driver+monitor could have objections too, i see no issue in that some "component" says "please do not stop now"

#4 this is more work to add raise+drop to every sequence body it is simpler to do something like:

virtual class uvm_active_sequence #(type A,type B=A) extends uvm_sequence#(A,;
    // ctor
    function pre_body(); uvm_test_done.raise_objection(...); endfunction
    functionpost_body(); uvm_test_done.drop_objection(); endfunction
endclass

AXI Protocol

 Exclusive access process
:- The basic process for an exclusive access is: 1. A master performs an exclusive read from an address location. 2. At some later time, the master attempts to complete the exclusive operation by performing an exclusive write to the same address location. 3. The exclusive write access of the master is signalled as: • Successful if no other master has written to that location between the read and write accesses. • Failed if another master has written to that location between the read and write accesses. In this case the address location is not updated. Note A master might not complete the write portion of an exclusive operation. The exclusive access monitoring hardware must monitor only one address per transaction ID. Therefore, if a master does not complete the write portion of an exclusive operation, a subsequent exclusive read changes the address that is being monitored for exclusivity.


At some time after the exclusive read, the master tries an exclusive write to the same location. If the location has not changed since the exclusive read, the exclusive write operation succeeds. The slave returns the EXOKAY response, and the exclusive write updates the memory location. If the address location has changed since the exclusive read, the exclusive write attempt fails, and the slave returns the OKAY response instea

The exclusive access monitor records the address and ARID value of any exclusive read operation. Then it monitors that location until either a write occurs to that location or until another exclusive read with the same ARID value resets the monitor to a different address. When an exclusive write occurs with a given AWID value then the monitor checks to see if that address is being monitored for exclusivity. If it is, then this implies that no write has occurred to that location, and the exclusive write proceeds, completing the exclusive access. The slave returns the EXOKAY response to the master. If the address is no longer being monitored at the time of an exclusive write, this implies one of the following: • the location has been updated since the exclusive read • the monitor has been reset to another location. In both cases the exclusive write must not update the address location, and the slave must return the OKAY response instead of the EXOKAY response.



SLVERR Slave error is used when the access has reached the slave successfully, but the slave wishes to return an error condition to the originating master.

DECERR Decode error is generated typically by an interconnect component to indicate that there is no slave at the transaction address.

Write Interleaving :-
when multiple masters are connected, suppose master1 and master2 wants to perform a write transaction to the same slave then
Master1 with burst of 4 and Master2 with a burst 8

Master1 Master1 Master2 Master2 Master2 .. . Master1 Master1

which means that as the both the masters are accessing the same slave, when Master1 is in idle state during the transaction then interconnect will perform the Master2 transaction.

The write data interleaving depth is the number of different addresses that are currently pending in the slave interface for which write data can be supplied. For example, a slave with a write data interleaving depth of two that has four different addresses, all with different AWID values, pending can accept data for either of the first two pending addresses. The order in which a slave receives the first data item of each transaction must be the same as the order in which it receives the addresses for the transactions. Write data interleaving can prevent stalling when the interconnect combines multiple streams of write data destined for the same slave. The interconnect might combine one write data stream from a slow source and another write data stream from a fast source. By interleaving the two write data streams, the interconnect can improve system performance.


OUT of order transfer:-

"Out-of-order" is a term usually referring to slaves, not masters. Slaves can return read data in a different order to that the addresses were received (if the IDs are different), or they can return BRESP write responses at the end of the write data transfers, again in a different order to that of the addresses, if the IDs are different.

Masters can interleave write data to the 2 different slaves (where IDs are unique), but this would be done because the master has that data available, not because it knows a specific slave can accept that data. If this particular data happens to be for your slower slave, WREADY will be driven low from that slave to stall the master until the slave is able to accept that data, and this will stall all data transfers from that master.

However when designing the interconnect logic linking your master to the 2 slaves, and if you knew slave #2 was slow, you could implement some sort of write data buffer on the interconnect output port driving slave #2 so that the buffer fills up quickly with the master data, and then slowly empties at the slave's data rate, thus not impacting on the master..


Locked transfer and exclusive transfer :- 

UVM interview questions and answers

How many phases UVM has explain each :-

1. We call run_test (if you don’t remember, see the line 17 of the top module in Tasting), which in turn calls the run_test task of the uvm_root class.
2. The uvm_root calls the m_run_phases task of the uvm_phase class.
3. For each phase, the execute_phase task is called.
4. If the phase is a top-down or bottom-up phase, exec_func is called for each component.
5. For example, the exec_func calls the build_phase function of each component.
6. If the phase is a task phase, exec_task is called for each component.
7. For example, the exec_task calls the main_phase task of each component.
8. The uvm_phase checks if any objections are raised by the components. The phase_done is the uvm_objection object that the uvm_phase keeps track of the number of objections with. When we called phase.raise_objection() from inside the run_phase of the jelly_bean_test class (see the line 27 of the jelly_bean_test class in Tasting), phase_done.raise_objection() is called in the uvm_phase under the hood.
9. If no objection is raised, all the processes started by the exec_task are killed. In other words, unless an objection is raised, the phase is immediately killed!
10. The steps 3 to 9 repeat until all phases are executed.

Why Final_phase is toptodown();

The final_phase() exists in UVM only for arrangements which run multiple loops around run..extract..check..report phases in a loop and then jump back to run() for the next iteration of multiple concatenated tests. Support for this is only partially defined or implemented in UVM today and is unlikely to be widely used in the industry (I would not recommend it for any use model that I am aware of).
However if this technique is used, there is a need for a final_phase() which is guaranteed to be the last phase before simulation exits, unlike report_phase() which may loop back. Why top-down? If one used this looped multiple test arrangement, final_phase() would be used for any cleanup required outside the loop, and hence it is top down, to ensure control from the topmost level of your test environment of that multiple test loop

Why build phase and connect phase is top to down and bottom to up ?

The build_phase has to be top-down because the parent component creates the child components (not the other way around). It also allows the parent component to configure the child components. On the other hand, the connect_phase, for example, is bottom-up. It allows the parent component to verify that the child components are connected properly.

http://cluelogic.com/2014/08/uvm-tutorial-for-candy-lovers-phasing/

How objection mechanism works 

How virtual sequence and virtual sequencer works ?

What is new,create ,build ?

• The new function creates an object of jelly_bean_agent. It also creates the handles for uvm_analysis_port, jelly_bean_sequencer, jelly_bean_driver, and jelly_bean_monitor. However, these handles are null because we have not created the objects for them yet.
• The build_phase function creates the components mentioned above. We called new to create an object of uvm_analysis_port. However, we called create to create the other components in case we want to override the component type later.
• The create function asks the UVM factory to create an object. The UVM factory knows which component to create even if the component type is overridden. The factory (or to be precise, uvm_component_registry) will call new on behalf of you.

How TLM works ?

Assertion Basics

System Verilog Assertion:-

Concurrent Assertion:-

Concurrent assertions are the work horses of the assertion notation. They must be clocked, either by specifying a clock edge with the assertion or by deriving a clock edge specification from a surrounding statement. Clocking is the key, because the evaluation of concurrent assertions starts every clock cycle with a new incarnation of a checker.

Example :- assert property @(posedge clk)

  a |=> b ##1 c ;

   endproperty

Concurrent assertions can also occur in sequential code. Here, they derive the synchronization and activation from the surrounding always block.

always_ff @(posedge clk) case (state) s0 : state <= s1; assert property ($past(state) = s4);

Sequence :-

Boolean expression events that evaluate over a period of time involving single/multiple clock cycles. 

Property :-

A number of sequences can be combined logically or sequentially to create more complex sequences. 

Assert :-

The property is the one that is verified during a simulation. It has to be asserted to take effect during a simulation

Operator information :-

•  and : When both sequence are expected to match, and both the sequence start at same time, but are not expected to finish at same time. Then and operator is used.
• intersect : When both sequence are expected to match, and both the sequence start and end at same time. Then intersectoperator is used.
• or : When one of the both sequence are expected to match. Then or operator is used.

UVM_DRIVER and UVM_SEQUENCER communication

To understand UVM_DRIVER and UVM_SEQUENCER relationship we need to first understand how uvm_driver and uvm_sequencer are coded in uvm library . 

UVM_DRIVER :-

class uvm_driver #(type REQ=uvm_sequence_item,

type RSP=REQ) extends uvm_component;

uvm_seq_item_pull_port #(REQ, RSP) seq_item_port;

uvm_analysis_port #(RSP) rsp_port;

REQ req;RSP rsp;.......endclass

In the above code we can see uvm_driver has seq_item_port which is pull type port . this port is used

to connect to the sequencer 
some time interviewer asks what kind of transfer method driver and sequencer use .we can see in

the above code uvm_seq_item_pull_port #(REQ, RSP) seq_item_port; this tell it is a pull type method . 

UVM_SEQUENCER :-

class uvm_sequencer #(type REQ=uvm_sequence_item, RSP=REQ)

extends uvm_sequencer_param_base #(REQ, RSP);
uvm_seq_item_pull_imp #(REQ, RSP, this_type) seq_item_export;


Above uvm_sequencer code we can see that sequencer is using seq_item_export to get connect with the driver .because this is pull type transfer , port will make a request of data and than export will provide the data . Driver and sequecer get connect in agent .

example :- drv.seq_item_port.connect(seqr.seq_item_export)

How transaction start and reach to driver :-

1. Driver will request for data using get_next_item , in the same time sequencer will check  for the
sequence which is started from the test case.
2. Once sequnce is started , by using arbitration sequencer will give a grant .
3. Sequence job is to select the sequence and give a grant based on the priority
4. Once grant is done Start_item will be execute because it was waiting for grant .
5. From the Finish Item ,data will be flowing to driver and will hold the process till
item_done recived from the driver .
I have captured this information directly from the uvm_driver , sequencer , sequence_base
class if you want in more details can check or relate in the following links
http://www.studio-muzzi.com/project/docs/UVMdocs_smu/uvm-1.1d/uvm__sequence__base_8svh_source.html
http://www.studio-muzzi.com/project/docs/UVMdocs_smu/uvm-1.1d/uvm__sequencer_8svh_source.html
http://www.studio-muzzi.com/project/docs/UVMdocs_smu/uvm-1.1d/uvm__driver_8svh_source.html

DDR interview question

1. What is SDRAM ? 

SDRAM is high-speed Dynamic Random Access Memory (DRAM) with a synchronous interface. The synchronous interface and fully pipelined internal architecture of SDRAM allow extremely fast data rates if used efficiently. SDRAM is organized in banks of memory addressed by row and column. The number of row and column address bits depends on the size and configuration of the memory.  Synchronous meaning there will be a clock and data relationship.

2. How data is written and read in the SDRAM? 
The memory cell is written to by placing a “1” or “0” charge into the capacitor cell. This is done during a write cycle by opening the cell transistor (gate to power supply or VCC) and presenting either VCC or 0V (ground) at the capacitor. The word line (gate of the transistor) is then held at ground to isolate the capacitor charge. This capacitor will be accessed for either a new write, a read, or a refresh.

3. How Row Address and Column Address access happen in SDRAM ?

First Step: Row Addresses Row addresses are present on address pads and are internally validated by the RAS (Row Address Access) clock. A bar on top of the signal name means this signal is active when it is at a low level. The X addresses select one row through the row decode, while all the other non-selected rows remain at 0V. Each cell of the selected row is tied to a sense amplifier. A sense amplifier is a circuit that is able to recognize if a charge has been loaded into the capacitor of the memory cell, and to translate this charge or lack of charge into a 1 or 0. There are as many sense amplifiers as there are cells on a row. Each sense amplifier is connected to a column (Y address). In this first step all the cells of the entire row are read by the sense amplifier. This step is long and critical because the row has a high time constant due to the fact that it is formed by the gates of the memory cells. Also, the sense amplifier has to read a very weak charge (approximately 30 femtoFarads or 30fF).

Second Step: Column Addresses Following the first step, column addresses are present on the address pads and are internally validated by the Column Address Access (CAS) clock. Each selected memory cell has its data validated in a sense amplifier. Column access is fast. This step consists of transferring data present in the sense amplifier to the Dout pin through the column decode and the output buffer. On memory data sheets, the access time from RAS is termed tRAC and the access time from CAS is listed as tCAC. On a typical standard DRAM of 60ns access time, tRAC = 60ns and tCAC = 15ns.

4. What refresh command does in SDRAM ?

The word “DRAM” is an acronym for Dynamic Random-Access Memory. The nature of the non- persistent charge storage in the DRAM cells means that the electrical charge stored in the storage capacitors will gradually leak out through the access transistors. Consequently, to maintain data integrity, data values stored in DRAM cells must be periodically read out and restored to their respective  the DRAM the row address from the refresh address register and then sends the same row address to all banks to be refreshed concurrently.  the single refresh command to all banks takes one refresh cycle time tRFC to complete

5. How Read cycle complete in SDRAM ?
Read get complete in three steps
1. Row access command
2. column read
3. Precharge
Each Row access command brings all the data bits to the array of sense amplifier in given bank . Then by the column access read command these data bits brings to the memory controller through data bus .

Then, after tRAS time from the initial issuance of the row access command, the DRAM cells are ready for a precharge command to reset the bitlines and the sense amplifi ers. Collectively, memory systems that immediately precharge a bank to prepare it for another access to a different row are known as close-page memory systems. Memory systems that keep rows active at the sense amplifi ers are known as open-page memory systems

6. Write cycle For DRAM ?

In the case of a write access, data must be provided by the memory controller, driven through the data bus, passed through the I/O gating multiplexors, overdrive the sense amplifi ers, and fi nally stored into the DRAM cells. This complex series of actions must be completed before the precharge
command that completes the sequence can proceed.

7. How DDR read command completed?
READ bursts are initiated with a READ command.  The starting column and bank addresses are provided with the READ command and AUTO PRECHARGE is either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the row that is accessed will start precharge at the completion of the burst.

During READ bursts, the valid data--out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data--out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of CK and CK).  DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last data--out element is known as the read postamble.

8. How DDR write command completed?

The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0--Ai, selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/ column location.

9.  Why active command is Needed?

Activate command is used to active the ROW, without active, we can't do any read or write operation.
First, activate command issued, BA0-1 tell the bank info and A0-10 tell the ROW info, once the row is activated then only the row is ready for any kind of data transfer.

10 .  What is the precharge command?

 The precharge command completes the row access sequence as it resets the sense amplifi ers and the bitlines and prepares them for another row access command to the same array of DRAM cells

The two row-access-related timing parameters, tRP and tRAS, can be combined to form tRC, the row cycle time. The row cycle time of a given DRAM device denotes the minimum amount of time that a DRAM device needs to bring data from the DRAM cell arrays into the sense amplifi ers, restore the data to the DRAM cells, and precharge the bitlines to the reference voltage level for another row access command. The row cycle time is the fundamental limitation to the speed at which data can be retrieved from different rows within the same DRAM bank. As a result, tRC is also commonly referred to as the random row-cycle time of a DRAM device.

11.  How AUTO PRECHARGE  command is issued?

AUTO PRECHARGE is a feature which performs the same individual--bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command.

12.  Difference between auto refresh and self Refresh?

self-refresh mode is nothing but just a standby mode, so that data is not lost when external clock is not there.. it is purely to save power consumption..  CKE is high during the self refresh case .

DLL is automatically off and on based on the enter and exit of self refresh command . 

Auto-refresh mode auto refreshing of data happens every pre-defined time intervals.. usually a command is there to enter self refreshing mode. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 * tREFI.

13. what is ODT ?

On die termination ODT is typically required as the speeds increase into the DDR2 and DDR3 range. The impedance of the ODT is typically a trade-off between signal integrity and power consumption. In most cases, the Rtt value is slightly higher in comparison with the RON value of the DRAM. By doing this, the signaling will not be as clean, but the gain in voltage margin helps close timing. An even higher Rtt can be chosen to reduce power like 150Ω. The real question comes down to whether it’s good enough to still close timing and to burn as little power as possible.

14. How write leveling is done ?

IFor better signal integrity, DDR3 SDRAM memory modules have adopted fly-by topology for the commands, addresses, control signals, and clocks. Write leveling is a scheme for the memory controller to adjust or de-skew the DQS strobe (DQS, DQS#) to CK relationship at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is generally used as part of the initialization process, if required. For normal DRAM operation, this feature must be disabled. This is the only DRAM operation where the DQS functions as an input (to capture the incoming clock) and the DQ function as outputs (to report the state of the clock). Note that nonstandard ODT schemes are required.

The memory controller using the write leveling procedure must have adjustable delay settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins. This is accomplished when the DRAM asynchronously feeds back the CK status via the DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the DQS strobe until a CK transition from 0 to 1 is detected. The DQS delay established by this procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that use fly-by topology by de-skewing the trace length mismatch. A conceptual timing of this procedure is shown in

When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ outputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ0 with all other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for the lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS and UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on a x16 enable each byte lane to be leveled independently.

15. What are the most timing parameter and there definitions ?

• CL: CAS Latency. The time it takes between a command having been sent to the memory and when it begins to reply to it. It is the time it takes between the processor asking for some data from the memory and then returning it.
• tRCD: RAS to CAS Delay. The time it takes between the activation of the line (RAS) and the column (CAS) where the data are stored in the matrix.
• tRP: RAS Precharge. The time it takes between disabling the access to a line of data and the beginning of the access to another line of data.
• tRAS: Active to Precharge Delay. How long the memory has to wait until the next access to the memory can be initiated.
• CMD: Command Rate. The time it takes between the memory chip having been activated and when the first command may be sent to the memory. Sometimes this value is not announced. It usually is T1 (1 clock cycle) or T2 (2 clock cycles).

 17. What is read leveling in DDR3 ?

Read leveling addresses the skew between data and strobes for read data transactions. To support this feature, DDR3 memories incorporate a Multi Purpose Register (MPR) which contains a predefined data pattern which, when selected, is output on the data lines, instead of normal data from the memory array. Before starting the read leveling sequence, the MPR data is selected as output by programming appropriate mode register. Thereafter read leveling is initiated by giving READ command to the memory module and trying to capture the pre-defined data by optimally adjusting the internal delays on data strobes. This process is repeated till the internal delays on the data strobes are adjusted to create a proper window for best capture the pre-defined data pattern. In normal read write operation DQ is in middle of dqs but in read leveling data will at the edge of DQS .  Read leveling can be seen only in high speed DDR3 like DDR3 1600 where the clock is in fastest speed. 

18.  what is ZQ Calibration ?

The ZQ CALIBRATION LONG (ZQCL) command is used to perform the initial calibration during a power-up initialization and reset sequence . This command may be issued at any time by the controller, depending on the system environment. The ZQCL command triggers the calibration engine inside the DRAM. After calibration is achieved, the calibrated values are transferred from the calibration engine to the DRAM I/O, which are reflected as updated RON and ODT values. The DRAM is allowed a timing window defined by either tZQinit or tZQoper to perform a full calibration and transfer of values. When ZQCL is issued during the initialization sequence, the timing parameter tZQinit must be satisfied. When initialization is complete, subsequent ZQCL commands require the timing parameter tZQoper to be satisfied.

19. what is ZQ CALIBRATION SHORT  ?

The ZQ CALIBRATION SHORT (ZQCS) command is used to perform periodic calibrations to account for small voltage and temperature variations. A shorter timing window is provided to perform the reduced calibration and transfer of values as defined by timing parameter tZQCS. A ZQCS command can effectively correct a minimum of 0.5% RON and RTT impedance error within 64 clock cycles

20 . Basic DDR initialization sequence ?

DDR has a basic init sequence in all configuration but each DDR model will may have some change as per there speed and configuration

1. Apply power. RESET# is recommended to be below 0.2 × VDDQ during power ramp to ensure the outputs remain disabled (High-Z) and ODT off (RTT is also High-Z). All other inputs, including ODT, may be undefined.
2. Until stable power, maintain RESET# LOW to ensure the outputs remain disabled (High-Z). After the power is stable, RESET# must be LOW for at least 200µs to begin the initialization process. ODT will remain in the High-Z state while RESET# is LOW and until CKE is registered HIGH.
3. CKE must be LOW 10ns prior to RESET# transitioning HIGH.
4. After RESET# transitions HIGH, wait 500µs (minus one clock) with CKE LOW.
5. After the CKE LOW time, CKE may be brought HIGH (synchronously) and only NOP or DES commands may be issued. The clock must be present and valid for at least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least t IS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be continuously registered HIGH until the full initialization process is complete.
6. After CKE is registered HIGH and after tXPR has been satisfied, MRS commands may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable settings (provide LOW to BA2 and BA0 and HIGH to BA1).
7. Issue an MRS command to MR3 with the applicable settings.
8. Issue an MRS command to MR1 with the applicable settings, including enabling the DLL and configuring ODT.
9. Issue an MRS command to MR0 with the applicable settings, including a DLL RESET command. tDLLK (512) cycles of clock input are required to lock the DLL.
10. Issue a ZQCL command to calibrate RTT and RON values for the process voltage temperature (PVT). Prior to normal operation, tZQinit must be satisfied.
11. When tDLLK and tZQinit have been satisfied, the DDR3 SDRAM will be ready for normal operation

21. How can be internal clock frequency change ?

during self refresh entry and precharge power down mode . During the input clock frequency change, CKE must be held at a stable LOW level. When the input clock frequency is changed, a stable clock must be provided to the DRAM tCKSRX before precharge power-down may be exited. After precharge power-down is exited and tXP has been satisfied, the DLL must be reset via the MRS. Depending on the new clock frequency, additional MRS commands may need to be issued. During the DLL lock time, RTT,nom and RTT(WR) must remain in an off state. After the DLL lock time, the DRAM is ready to operate with a new clock frequency